Xulong Tang

Welcome! I am an associate professor in the Department of Computer Science at the University of Pittsburgh. My research spans computer architecture and systems, with a focus on multi-GPU architectures, high-performance LLM infrastructure and systems, edge AI, and quantum systems. I received my Ph.D. from Penn State and Master from USTC.

Contact: 210 S. Bouquet Street, SENSQ 6115. Department of Computer Science, University of Pittsburgh, Pittsburgh, PA, 15213
Email: tax6 AT pitt DOT edu

Curriculum Vitae

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DBLP

Research

My research interests lie in the area of both compiler and computer architecture. More specifically, my group works on software-hardware co-designs for emerging applications, exploring algorithm-level innovations and advanced architecture designs. My current research focuses on the following projects:

Feuling machine learning and deep learning applications at scale on single- and multi- GPU systems.

Exploring machine learning and DNN characteristics and algorithm innovations.
Developing efficient compiler optimizations and runtime management.
Designing architectures and system features toward next-generation GPU systems.

Building efficient quantum computing simulation Eco-system.

Leveraging innovative system optimizations to simulate large and complex quantum circuits.
Developing both front-end and back-end quantum compiler supports for complex quantum circuits.
Building software-hardware co-optimizations for domain-specific (e.g., quantum chemical applications) quantum applications.
Exploring heterogeneous system designs that consists of quantum devices and classical devices.

A Software and Hardware Co-Design for Addressing the Performance Bottlenecks in Secure Non-Volatile Memory

Developing zero-copy page remapping and parallel remapping and computation techniques for SGX.
Developing compiler-assisted user controlled paging.
Designing high performance persistence support in secure NVM.

Some past research projects during my Ph.D:

Optimizing Dynamic parallelism for irregular applications on GPGPUs.

Designed a runtime control system which dynamically decide the child kernel launch. Such a control system allows a better mix of dynamically generated child kernels and parent kernels for the scheduler to effectively hide the launch overheads and improve the utilization of the GPU resources.
Analyzed data reuse and designed locality-aware scheduler for dynamic parallelism.

Compiler-assisted optimization on manycore platforms.

Proposed a loop iteration scheduling strategy which considers both bank-level parallelism (from an inter-core perspective) and bank reuse (from an intra-core perspective) for irregular applications.
Designed a compiler algorithm that partitions the computations in a given loop nest into subcomputations and schedules the resulting subcomputations on manycore system with the goal of reducing the distance-to-data on the on-chip network.

Xulong Tang

Research

Experience